General protection fault

This article is about the error. For the web comic, see General Protection Fault (comic).

A general protection fault in the Intel x86 architecture is a fault which can encompass several cases, where protection mechanisms within the architecture are violated by the program that is running upon the architecture, whether it be the kernel or user program.

General protection faults can occur for several reasons, including:

• segment limits exceeded
  • with CS, DS, ES, FS, or GS,
  • accessing descriptor tables (such as the GDT/IDT/LDT),
• segment permissions violated
  • jumping to nonexecutable segments
  • writing to code or read only segments
  • reading execute-only segments
• segments illegally loaded
  • stack segment (SS) loaded with a segment selector for a read only, executable, or null segment
  • code segment (CS) loaded with a segment selector for a data or null segment.
  • SS, DS, ES, FS, GS, loaded with a segment selector for a system segment
  • DS, ES, ES, FS, GS, loaded with a segment selector for an execute-only code segment
• accessing memory using DS, ES, FS, or GS, when they contain a null selector
• switching (TSS)
  • switching to a busy task during a call or jump
  • switching to an available task during IRET
  • using a segment selector on switch pointing to a TSS descriptor in the LDT
• miscellaneous
  • attempting to access an interrupt/exception handler from v86 mode when the handler's code segment DPL is greater than 0.
  • attempting to write a 1 into the reserved bits of CR4
  • attempting to execute privileged instructions when the current privilege level (CPL) is not zero
  • writing to a reserved bit in a MSR
  • accessing a gate containing a null segment selector
  • executing a software interrupt when the CPL is greater than the DPL set for the interrupt gate
  • the segment selector in a call, interrupt or trap geate do not point to a code segment
  • exceeding the instruction length of 15 bytes
  • violating privilege rules
  • enabling paging whilst disabling protection
  • referencing IDT following an interrupt or exception that is not an interrupt, trap, or task gate

Reference: Intel Architecture Software Developer's Manual Volume 3: System Programming

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