Phase-locked loop

electronic systems use internal clocks which are required to be phase-aligned to and/or frequency multiples of some external reference clock. For example, a typical PC CPU might have an internal 2.4 GHz clock which is phase aligned to a bus clock running at 100 MHz. The frequency multiplication is important because multiplying frequencies on chip is much easier than transmitting 2.4 GHz clocks on a motherboard. The phase alignment is important so that data can be exchanged reliably between circuits in the 2.4 GHz core domain and circuits in the 100 MHz bus clock domain.

Typically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system's clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input. The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched.

PLLs are ubiquitous -- they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same frequency as the clock driven through the clock distribution, other times the distributed clock may be some rational multiple of the reference.

PLLs are generally built of a phase frequency detector, a charge pump, low pass filter, bias generator, voltage-controlled oscillator (VCO), and usually some kind of output converter. There may be a divider in the feedback path or in the reference path, or both, in order to make the PLL's output clock a rational multiple of the reference.

One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset. The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible.

Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated. This is called supply and substrate noise rejection.

Phase-locked loops are widely used for synchronization purposes; in space communications for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization.

Phase-locked loops can also be used to demodulate frequency-modulated signals, and to synthesize new frequencies which are a multiple of a reference frequency.

An important part of a phase-locked loop is the phase detector. This compares the phase of the local oscillator to that of the reference signal. In an analog PLL the phase detector is a linear multiplier. This generates a low-frequency signal whose amplitude is related to the phase difference, or phase error, between the oscillator and the reference, and an unwanted high-frequency signal that is filtered out.

There are several types of phase detectors used in digital phase-locked loops. The simplest is an exclusive OR gate, which maintains a 90° phase difference, but cannot lock the signal unless it is already on frequency. A more complicated one uses flip-flops to determine which of the two signals has a zero-crossing earlier or more often. This brings the signal in even when it is off frequency.

Analog phase-locked loop

The equations governing a phase-locked loop are the following:

<math>x_m(t) = x_c(t) \cdot x_r(t)<math>

<math>\omega_r(t) = \omega_f + g_v y(t)<math>

<math>x_r(t) = A_r \cos\left( \int \omega_r(\tau)\, d\tau \right)

where

<math>\phi = \int g_v y(\tau)\, d\tau<math>

the input to the PLL is <math>x_c(t)<math>, the output of the voltage-controlled oscillator (VCO) is <math>x_r(t)<math>, the output of the phase detector is <math>x_m(t)<math>. The input to the loop filter is <math>x_m(t)<math>, the output is <math>y(t)<math>. Note that <math>g_v<math> is the sensitivity of the VCO and is expressed in Hz/V.

We can deduce how the PLL reacts to a sinusoidal input signal:

<math>x_c(t) = A_c \sin(\omega_c t).<math>

The output of the phase detector then is:

<math>x_m(t) = A_c \sin( \omega_c t ) A_r \cos(\omega_f t + \phi).<math>

This can be rewritten into sum and difference components using trigonometric identities:

<math>x_m(t) = {A_c A_f \over 2} \sin( \omega_c t - \omega_f t - \phi )

<math> Filtering out the sum frequency and leaving the difference frequency, enables us to derive a small-signal model of the phase-locked loop. If we can make <math>\omega_f \approx \omega_c<math>, then the <math>\sin(\cdot)<math> can be approximated by its argument: <math>- A_c A_f \phi / 2<math>. The phase-locked loop is said to be locked if this is the case.

Some parts of this article are derived from public domain parts of Federal Standard 1037C in support of MIL-STD-188.